The present invention relates to a MOS (Metal-Oxide Semiconductor) device. Particularly, this invention relates to a common source MOS device for high frequencies.
High power gains have recently been required for common source MOS devices for high frequencies. This requirement is satisfied by providing such MOS devices with configuration of thin film SOI (Silicon On Insulator) with a semiconductor layer (an active region) of some 10 nm. These SOI-type MOS devices have a completely depleted active region (a layer over an insulation layer in SOI configuration) under a channel region to reduce depletion layer capacity and junction capacity and also output capacity that is one of parameters to decide power gain.
FIG. 1 shows a conventional SOI-type MOS device for high frequencies. In FIG. 1, the MOS device has the SOI configuration with a p-type semiconductor substrate 101, an insulation layer 102 and a p-type semiconductor layer 103.
Formed on the SOI configuration are a n-type source and drain regions 104 and 105. A gate electrode 107 is formed above the semiconductor layer 103 via a gate oxide film 106 and between the source and drain regions 104 and 105. The drain region 105 is formed so that its portion reaches the insulation layer 102.
The surface of the semiconductor layer 103 except covered with the gate oxide film 106 is covered with a silicon oxide film 112. The gate electrode 107 is covered with a protective film 113 made of BPSG (Boron Phosho Silicate Glass).
Source and drain electrodes 110 and 111 are respectively formed on openings made in portions of the silicon oxide film 112 and the protective film 113 on the surface under which the semiconductor layer 103 and the source region 104 are next to each other and on the surface of the drain region 105.
The semiconductor layer 103 is avoided to be in floating-state by a connection between a portion of the surface of the source region 104 and that of the semiconductor layer 103 by means of the source electrode 110. A source-wiring 115 made of a fine wire is provided for grounding the source electrode 110.
As described above, the conventional SOI-type MOS device is provided insulation between the semiconductor substrate 101 and the semiconductor layer 103 by means of the insulation layer 102. This insulation requires that the semiconductor substrate 101 and the source electrode 110 be separately grounded for this type of MOS device to be applied to a common source MOS-FET (Field-Effect Transistor). The source electrode 110 is thus connected (grounded) to the semiconductor substrate 101 via the wiring 115. This causes a problem in that the inductance of the wiring 115 becomes equal to the ground inductance and hence reduces power gains for high frequencies.